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DDR-SDRAM-CTRL

Up to 64-bit LPDDR Controller for Altera FPGA

Description
Specifications
The Alma Technologies DDR-SDRAM-CTRL core provides a simplified, pipelined and burst-optimized interface to industry standard LPDDR SDRAM devices for Altera Cyclone III/IV/V, Arria II/V and Stratix II/III/IV/V FPGA. The distinctive characteristics of this core are:

Ease-of-use − All required management, initialization, address and burst handling procedures are done by the controller. Furthermore control, write-data and read-data paths are split, enabling higher performance and easier integration. The controller is also available as an Altera Qsys component with Avalon-MM slave interface.

Performance The controller achieves maximal memory bandwidth utilization through the use of pipelined and parallel architectural design practices.

Flexibility − All memory parameters are optionally runtime programmable.

Being carefully designed and rigorously verified, the DDR-SDRAM-CTRL is a reliable and easy-to-use and integrate core.


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