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DDR-SDRAM-CTRL

Up to 64-bit LPDDR Controller for Altera FPGA

Description
Specifications

Interfaces to all industry standard LPDDR chips

High-performance architecture, with a three-stage processing queue for maximal bandwidth utilization

Pipelined design achieves ease of integration and high-clock rates

Incorporates a programmable auto-precharge mechanism

Incorporates a programmable automatic refresh policy

Runtime programmable memory parameters



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