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Single Data Rate Mobile SDRAM Controller


Supports up to 2G address space, 1 to 8 chip-selects, 2 to 4 banks, 11 to 14 row bits and 8 to 12 columns bits.

Supports all standard SDRAM chips and registered/unbuffered DIMMs.

Access cascading and efficient back management enable up to 100% utilization of the memory throughput.

Programmable auto-refresh policy, in order to minimize overhead.

Runtime-configurable timing parameters (CAS latency, tRP, tRCD, tREFC, tMRD, ...).

Runtime-configurable memory settings (Row bits, Column bits, Bank bits, number of CSs).

Runtime configurable Mobile-SDR support and Extended-Mode-Register (EMR).

Bank status monitoring.

Configurable auto-close mechanism.

Configurable auto power-down and auto-self-refresh.

Supports sleep-mode.

Flexible user-interface, with separate read and write interfaces, which support from single to any arbitrary length burst accesses.

Can be easily interfaced to legacy on-chip synchronous microprocessor busses that support burstaccesses and handshaking or to on-chip FIFOs.

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