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8-bit SpeedView Enabled Baseline JPEG Encoder

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The Alma Technologies SVE-JPEG-E core is a standalone and high-performance JPEG encoder for still image and video compression applications that produces both JPEG Baseline and SpeedView™ enabled JPEG data streams.

One of the fastest available JPEG encoders, the SVE-JPEG-E can encode at Full HD (1080p30) or higher rates, even in FPGA devices. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the SVE-JPEG-E core ideal for interoperable systems and devices.

SVE-JPEG-E block diagram | Alma Technologies

Integrating the Scalado SpeedTags™ technology the SVE-JPEG-E outputs compressed streams that are compatible with SpeedView™, a member of Scalado's CAPS™ imaging suite which is focused on providing enhanced functionality to camera equipped mobile devices.

In addition to generating standalone Baseline or SpeedView™ enabled JPEG streams, the core is also capable of producing the (de facto) standard video payload of many motion JPEG container formats. Furthermore, bandwidth-constraint applications can benefit from the included programmable bit-rate control block.

The core is designed with easy-to-use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the SVE-JPEG-E is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.

IP Deliverables

Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for Intel, Lattice, Microsemi and Xilinx FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Self checking testbench environment, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Specifications »

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