The Alma Technologies SVE-JPEG-E core is a standalone and high-performance JPEG encoder for still image and video compression
applications that produces both JPEG Baseline and SpeedView™ enabled JPEG data streams.
One of the fastest available JPEG encoders, the SVE-JPEG-E can encode at Full HD (1080p30) or higher rates,
even in FPGA devices. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG
standard makes the SVE-JPEG-E core ideal for interoperable systems and devices.
Integrating the Scalado SpeedTags™ technology the SVE-JPEG-E outputs compressed streams that are compatible with
SpeedView™, a member of Scalado's CAPS™ imaging suite which is focused on providing enhanced
functionality to camera equipped mobile devices.
In addition to generating standalone Baseline or SpeedView™ enabled JPEG streams, the core is also
capable of producing the (de facto) standard video payload of many motion JPEG container formats.
Furthermore, bandwidth-constraint applications can benefit from the included programmable bit-rate control block.
The core is designed with easy-to-use, fully controllable and FIFO-like, streaming input and output interfaces.
Being carefully designed and rigorously verified, the SVE-JPEG-E is a reliable and easy to
integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
IP Deliverables
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Symbol
Features
Scalado CAPS™ Compliance
Integrates SpeedTags™ technology
Baseline ISO/IEC 10918-1 JPEG Compliance
Programmable Huffman Tables (two DC, two AC)
Programmable Quantization Tables (up to four)
Up to four color components
Supports all possible scan configurations and all JPEG formats for input and output data
Supports any image size up to 64K x 64K
Supports DNL and restart markers
Standalone, Baseline JPEG stream output
Additional Processing Capabilities
Programmable Quantization Quality (1 to 100)
Motion JPEG payload encoding
One-pass compression ratio regulation
Motion JPEG video oriented rate control option with programmable nominal output frame size and transmission buffer size in bytes Block-based, rate control option with independent Luminance and Chrominance thresholds
Ease of Integration
Registered I/O ports
Simple, microcontroller like, programming interface
High speed, flow controllable, streaming I/O data interfaces
Simple and FIFO like
Avalon-ST™ compliant (read latency 0)
Single clock per input sample processing rate
Fully programmable through standard JPEG marker segments
Automatic JPEG markers generation on the output
Automatic program-once encode-many operation
Easy System Implementation and Verification
Extensive documentation
Bit Accurate Model (BAM)
Test Vector generation
Self checking testbench environment
Sample BAM scripts
Synthesis scripts
Simulation scripts
Place & Route scripts for FPGAs
Trouble-Free Technology Map and Implementation
Fully portable HDL source code
No internal tri-states
Scan-ready design
Strictly positive edge triggered design using D-type only Flip-Flops
Fully synchronous operation
No need for special timing constraints
No false paths
No multi-cycle paths
No special handling paths
