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SIPDSC

Scalable architecture for a soft Intellectual Property core design implementing DSC 1.2a standard

Project Code:
T1EDK-00423
Timeframe:
2018 É 2020

The scope of this project (code: T1EDK-00423) is to research for a scalable performance architecture implementing the DSC standard in a digital Integrated Circuit design. This scalable architecture aims to extend the implementation performance in order to satisfy the needs of future applications with increasing resolutions and data transfer rates. Within the project, a DSC 1.2a standard encoder and decoder will be implemented based on the resulted scalable performance architecture, using Hardware Description Languages. The SIPDSC project is part of the specialized field 8.6.4. The main innovative element of this project is the resulted scalable performance architecture adapted to the demands of the DSC algorithm, which will lead to a competing IP core. In details, the project will focus on the following points:

Research on a scalable performance design methodology for ultra-high throughput Integrated Circuit design.

Research on a design and timing methodology for large amount of data transfer Integrated Circuit design.

Research on a design methodology that minimizes the power consumption and the footprint of the design.

Research on a verification methodology for the proper functional operation and performance of the design.

The project is co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH – CREATE – INNOVATE.

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