SHA256

Description
Specifications
The SHA256 core is a high performance implementation of the SHA-256 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-2. The core is composed of two main units, the SHA256 Engine and the Padding Unit as shown in the block diagram. The SHA256 Engine applies the SHA256 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.
The processing of one 512-bit block is performed in 66 clock cycles and the bit-rate achieved is 7.75Mbps / MHz on the input of the SHA256 core.

The SHA256 core is equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user's application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.

Applications


  Data integrity.
  Bulk Encryption.
  High speed networking equipment.
  Secure wireless applications.


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Alma Technologies announces the immediate availability of its new 12-bit Extended JPEG Decoder Core.
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Alma Technologies presented its silicon IP
(intellectual property) cores at VISION 2011

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Launch of new DDR - DDR2 Controller core.
"Innovation Center in Microelectronics" Inauguration Event.
Launch of new SDR-SDRAM Controller core.
Alma Technologies at IBC2013
Alma Technologies at VISION 2012
Alma Technologies at IBC2012
Alma Technologies at VISION 2011
https://www.alma-technologies.com/Data-Sheets/alma_technologies_image_video_2012_2013.pdf