The UHT-JPEG2K-E core is a scalable, ultra-high throughput, hardware JPEG 2000 encoder, designed to provide all the power needed in modern image and Ultra HD video compression applications that have to cope with massive pixel rates and resolutions.
This IP core supports lossy and numerically lossless encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) images or video streams with up to 16-bit per component color depth.
The UHT-JPEG2K-E is available for ASIC or Intel, Lattice, Microsemi and Xilinx FPGA and SoC based designs.
Using multiple internal compression engines, the UHT-JPEG2K-E offers the needed performance through its scalable parallel architecture. Each input image or video frame is split internally into pieces and each piece is allocated to one of the multiple internal compression engines. The encoded output streams of the compression engines are combined in a single output stream. These operations are done in a way that is transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components. The number of internal compression engines is configurable before synthesis, adapting to the implementation technology speed, and non-critical resources are shared between the multiple compression engines.
The UHT-JPEG2K-E IP Core is very easy to use and integrate in a system. A single uncompressed data input interface is used to accept raster scan pixels, and a single JPEG 2000 compliant byte stream is produced to the output. The operation of the core is completely standalone, without needing any host CPU or GPU power. The JPEG 2000 output byte stream can be decoded - as is - by any corresponding ISO/IEC 15444-1 JPEG 2000 compliant decoder.
The UHT-JPEG2K-E core features simple, fully controllable and FIFO-like, streaming input and output interfaces.
Being carefully designed and rigorously verified, the UHT-JPEG2K-E is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for Intel, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts