Image scaling is a process of constructing a resized image from a given input image. The constructed image can be smaller, larger, or equal in size, depending on the scaling ratio.
The UHT-SCALER core is an image scaler which provides a video processing block, that converts the input color images of one size to output color images of a different size.
It supports scaling of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) video streams, in 8 up to 16 bits sample depths and supports bilinear, bicubic, lanczos and expfilter scaling algorithms.
The UHT-SCALER core is a standalone and high-performance scaler, designed for enabling ultra-high frame rate SD and HD scaling, and Ultra HD video encoding (4K/8K and beyond), even in low-end ASIC or FPGA silicon.
The UHT-SCALER is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microsemi FPGA and SoC based designs.
The UHT-SCALER is very easy to use and integrate in a system. It requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can scale an arbitrary number of video frames without the need of any further intervention or assistance by the host system CPU.
Using multiple internal processing engines, the UHT-SCALER offers the needed performance through its scalable parallel architecture.
Each input image or video frame is split internally into chunks and each chunk is assigned to one of multiple internal processing units.
This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the
rest SoC components. The number of internal processing units is configurable before synthesis, adapting to the implementation technology speed,
and non-critical resources are shared between the multiple scaler engines.
The UHT-SCALER accepts the uncompressed raw video data in interleaved scan format and outputs scaled uncompressed raw video data in interleaved scan format.
No post processing on the output video data, other than (as examples) saving, muxing, or transmitting, is required by the host.
The UHT-SCALER core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces.
Being carefully designed and rigorously verified, the UHT-SCALER is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.
IP Deliverables
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Specifications »
Symbol
Features
Standalone Scaling Operation
Programmable image dimensions from 8 x 8 up to 64k x 64k
Supports YcbCr/RGB 4:4:4, YCbCr 4:2:2, YCbCr 4:2:0 and single-color 4:0:0 video formats
8 up to 16 bits per sample depth encoding
Support for bilinear, bicubic, lanczos and expfilter scaling algorithms
CPU-less, complete and standalone operation.
Advanced Scaling Implementation
Ultra-high throughput in low-end silicon
Ultra-low latency performance
On-chip memory implementation
Easy Implementation and Verification
Extensive documentation
Bit Accurate Model (BAM) with optional Test Vector generation functionality
Self-checking testbench environment
Sample BAM scripts
Synthesis scripts
Simulation scripts
Place & Route scripts for FPGAs
Trouble-Free Technology Map and Implementation
Self-contained RTL design
No internal tri-states
Strictly positive edge triggered design
D-type only Flip-Flops
Fully synchronous operation per clock domain1
Safe CDC transfers between clock domains2
No need for special timing constraints
No false or multi-cycle paths within the same clock domain
No CDC transfers that need to be specially constrained
No other specially constrained timing paths
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