The UHT-SCALER core provides an image and video processing block which converts input images of one size and sampling format to output images of a different size and/or sampling format. It supports scaling of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image streams with 8- up to 16-bit color depth, using the BILINEAR, BICUBIC, LANCZOS and EXPFILTER scaling methods. The UHT-SCALER is a standalone and high-performance scaler core, designed for enabling high-quality and ultra-high throughput performance, even in low-end target silicon technologies.
The UHT-SCALER is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
The core accepts the input image data in planar or interleaved scan order format and outputs the scaled image data in the same planar or interleaved format as the input.
The UHT-SCALER is very easy to use and integrate in a system. It requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can scale an arbitrary number of video frames without the need of any further intervention or assistance by the host system CPU.
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts