Scalable Ultra-High Throughput DSC 1.2b Decoder
The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.
The scalability of this IP core enables highly cost-effective silicon implementations of applications that need to handle massive pixel rates and resolutions.
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Bit Accurate Model (BAM) with optional Test Vector generation functionality
Self-checking testbench environment
Sample BAM scripts
Place & Route scripts for FPGAs