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UHT-JPEG-E

Scalable UHD JPEG Encoder − Ultra-High Throughput, 8/10/12-bit per component and CBR Motion JPEG video rate control

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The Alma Technologies UHT-JPEG-E IP Core is a very high performance 8-bit Baseline and 12-bit Extended JPEG encoder, designed to enable the massive pixel rates of 4K/8K UHD resolutions and high frame rate video applications in highly cost-effective FPGA and ASIC implementations.

The encoder is fully compliant to the ITU T.81 specification and supports encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) images or video streams, in 8-, 10- or 12-bit per component sample depths. The UHT-JPEG-E can be implemented using only on-chip memory resources, while using off-chip memory too is also natively supported. Designed with a user configurable architecture, the encoder scales to offer a sustained encoding throughput from 1 to 32 samples per clock cycle.



UHT-JPEG-E block diagram | Alma Technologies


Using multiple internal processing engines, the UHT-JPEG-E offers the needed performance through its scalable parallel architecture. Each input image or video frame is split internally into chunks and each chunk is assigned to one of multiple internal compression units. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components. The number of internal compression units is configurable before synthesis, adapting to the implementation technology speed, and non-critical resources are shared between the multiple compression engines.

The UHT-JPEG-E uses a single uncompressed data input interface - accepting raster scan pixels - and produces a single, ready-to-use and fully compliant JPEG stream output. The encoder employs also a constant bitrate video encoding option, making it a best fit for the bandwidth or storage constrained Motion JPEG video applications. Its operation is completely standalone, without needing any host CPU or GPU power. The output JPEG byte stream can be decoded, as is, by any standard compliant decoder.

The UHT-JPEG-E core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the UHT-JPEG-E is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.

IP Deliverables

Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Self checking testbench environment, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts



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