UHT™ Image & Video Compression IP
Alma Technologies features a separate product family of scalable Ultra-High Throughput JPEG, JPEG 2000 and H.264 image and video compression IP cores to address the ever-increasing resolution and frame rate needs of the imaging and videography industries, driven by the fast growing number of new applications that need to work with these new massive pixel rates.
The large amount of data produced by these applications makes compression even more significant, while the silicon requirements still need to remain within realistic and reasonably available levels. This new UHT™ series of Alma Technologies IP is designed to support the needed throughput and to offer uncompromised image quality at different levels of compression in mainstream, and highly cost-effective, FPGA or ASIC implementations.
Scalable and Transparent Parallel Processing
Powered by a configurable number of multiple internal processing engines, our scalable UHT™ IP cores bring all the speed needed today in the 4K/8K Ultra HD and High-Frame-Rate range of applications. Each input image or video frame is first split internally into chunks and each chunk is then assigned to one of the available parallel engines. This is done in a way which is totally transparent to the system utilizing the IP, as if a single encoding or decoding instance was used. Using always a single uncompressed data interface and a single, standard-compliant, compressed stream interface, the UHT™ IP cores abstract all the parallelization complexity from the rest SoC design and operation.
Silicon Resources Versatility
Packed with configurable expanded features and designed for silicon speed versus size versatility, our UHT™ IP cores optimize resource usage by leveraging resource sharing among their parallel engines. The number of the internal parallel engines itself is configurable before synthesis, matching the throughput requirements to the available silicon speed. Increasing the number of engines enables, for example, the encoding of UHD 4K/8K video even in low-end FPGA devices. Decreasing the number of engines, when a higher speed silicon is used, achieves the same with a much smaller silicon footrpint.