The Alma Technologies SPI-MEM-CTRL core is an advanced SPI serial NOR flash memory controller,
supporting Single, Dual and Quad I/O SPI accesses and including Boot and Execute on-the-fly features.
The SPI-MEM-CTRL controller automatically identifies a variety of serial NOR flash memories and communicates with the
memory device at the maximum possible bandwidth. Register accesses are used to insert memory access requests and to
read/write memory data from/to the SPI-MEM-CTRL core. Communication with devices other than those automatically
identified is also available as the core can be programmed by the user with the memory device parameters.
The SPI-MEM-CTRL can read, write or erase any part of the memory.
The SPI-MEM-CTRL controller has been rigorously verified. A complete verification environment that helps designers
verify the functionality and compliance of the core, including additional aids for system-level simulation, are available.
IP Deliverables
Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized and verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Symbol
Features
Device Independent:
Automatic identification of a variety of serial NOR flash memories
Configurable memory features to allow support for more serial flash devices
Efficient Bandwidth Utilization:
Automatic identification of maximum bandwidth access mode among:
single SPI
dual output SPI
dual I/O SPI
quad I/O SPI
Flexible Access Model:
Registered mapped I/O
Read access sizes from 1 byte up to memory density
Read accesses starting from any address offset
Write access sizes from 4 bytes up to memory density
Write accesses starting from any address offset that is a multiple of 4
Erasure of:
any sector (4KB)
any block (64KB)
whole chip
Ease of Integration:
Auto-detection of a wide set of serial flash devices to minimize programming overhead
Auto detection of the fastest way to read or program the memory, to maximize bandwidth and minimize programming overhead
Deep Power-down Mode support to minimize power consumption
Optional APB interface
Design Quality:
Robust verification with integrated self-checking testbench environment
Scan-ready design
