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8/10/12-bit Extended JPEG Decoder

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The JPEG-D-X core from Alma Technologies is a standalone and high-performance JPEG decoder for still image and video compression applications. Compliance┬╣ with the Baseline and the Extended Sequential DCT modes of the ISO/IEC 10918-1 JPEG standard makes this core suitable for interoperable systems and devices. The JPEG-E-X is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.

JPEG-D-X block diagram | Alma Technologies

In addition to decoding standard compliant Baseline and Extended JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.

The core is designed with simple, fully controllable and FIFO like, streaming input and output interfaces. Being carefully designed and rigorously verified, the JPEG-D-X is a reliable and easy-to-use and integrate IP.

IP Deliverables

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Notes :
┬╣Please refer to the Specifications tab for limitations with respect to the ISO/IEC 10918-1 JPEG standard.

Specifications »

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