category banner

SHA1

SHA-1 Secure Hash Function

Description
Specifications
Downloads
Get a Quote

The Alma Technologies SHA1 IP core is a high performance implementation of the SHA-1 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-1.



SHA1 block diagram | Alma Technologies


The core is composed of two main units, the SHA1 Engine and the Padding Unit as shown in the block diagram. The SHA1 Engine applies the SHA1 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.
The processing of one 512-bit block is performed in 82 clock cycles and the bit-rate achieved is 6.24Mbps / MHz on the input of the SHA1 core.

The SHA1 core is equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user's application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.



Applications

Data integrity.

Bulk Encryption.

High speed networking equipment.

Secure wireless applications.



 Page Top
© 2001-2017 Alma Technologies S.A.   All Rights Reserved.
Alma Technologies® is a trademark of Alma Technologies S.A. in the U.S., E.U. and/or other countries.
All other trademarks are the property of their respective owners.
windows logo
linux logo
keys icon