The Alma Technologies SHA1 IP core is a high performance implementation of the SHA-1 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-1.
The core is composed of two main units, the SHA1 Engine and the Padding Unit
as shown in the block diagram. The SHA1 Engine applies the
SHA1 loops on a single 512-bit message block, while the Padding Unit splits the input message into
512-bit blocks and performs the message padding on the last block of the message.
The SHA1 core is equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user's application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.
High speed networking equipment.
Secure wireless applications.