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MD5 Message-Digest Algorithm

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The Alma Technologies MD5 IP Core is a high-performance implementation of the MD5 Message-Digest algorithm, a one-way hash function, compliant to the RFC 1321 specification. The core is composed of two main units, the MD5 Engine and the Padding Unit. The MD5 Engine applies the MD5 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last message block.

MD5 block diagram | Alma Technologies

The processing of each 512-bit block is performed in 66 clock cycles and the bit-rate achieved on the input of the MD5 core is 7.75Mbps / MHz.

The MD5 core is equipped with easy-to-use, fully stallable interfaces both for input and output. These are designed to permit the userís application to pause the core output when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.

IP Deliverables

  Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized and verified Netlist
    for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices

  Release Notes, Design Specification and Integration Manual documents

  Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

  Self checking testbench environment, including sample BAM generated test cases

  Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

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