MD5
MD5 Message Digest Function
The Alma Technologies  The processing of each 512-bit block is performed in 66 clock cycles and the bit-rate achieved on the input of the MD5 core is 7.75Mbps / MHz. The MD5 core is equipped with easy-to-use, fully stallable interfaces both for input and output. These are designed to permit the user’s application to pause the core output when it is not able to receive data or to stop the input stream towards the core according to data arrival rate. IP DeliverablesClear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized and verified Netlist for Intel, Lattice, Microsemi and Xilinx FPGA and SoC devices Release Notes, Design Specification and Integration Manual documents Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts Self checking testbench environment, including sample BAM generated test cases Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts Symbol FeaturesCompliant, High-Performance and Standalone OperationCompliant to the RFC 1321 MD5 specification Message length up to 2^64-1 bits 66 processing cycles per 512-bit message block Bit padding implemented internally Input message length multiple of 8-bit Initial value of the chaining variables selected before synthesis High-speed, flow controllable, streaming I/O data interfaces Trouble-Free Technology Map and ImplementationFully portable, self-contained RTL source code Strictly positive edge triggered design D-type only Flip-Flops Fully synchronous operation No special timing constraints required No false paths No multi-cycle paths LiteratureMD5 Hash Function designer's manual Alma Technologies Silicon IP Cores Product Catalog (No registration required) Request a Quote for the |