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High Profiles H.264 Encoder − High 10, High 4:2:2 and High 4:4:4 (12-bit 4:2:2 or 4:2:0) Profiles

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Standard Compliant and Standalone Operation

Full compliance to the ITU-T H.264 specification

High 10, High 10 intra, High 4:2:2, High 4:2:2 intra, High 4:4:4 (12 bit 4:2:2 or 4:2:0), and High 4:4:4 intra (12 bit 4:2:2 or 4:2:0) profiles encoding

Multi-format 4:2:0 and 4:2:2 YCbCr digital video input

8-, 10- and 12-bit per component sample depth encoding

ITU-T H.264 Annex B compliant NAL byte stream output

Profile Level up to 5.2

No host CPU assisted, standalone operation

Advanced H264 Implementation

16 video lines algorthmic encoding latency

True H.264 compression efficiency and perceptually optimized Image Quality

Advanced Motion Estimation

Full search

Variable block size

Full, half and quarter pixel

Up to 4 motion vectors per macroblock

Advanced Intra prediction

All 4 Intra 16x16 prediction modes

All 4 Intra Chroma prediction modes

All 9 Intra 4x4 prediction modes

Intra in P (all prediction modes are always examined)

High throughput implementation: Sustained 2.5 (4:2:0) or 2.75 (4:2:2) clock cycles per pixel worst case processing rate

CABAC or CAVLC entropy coding

CQP - VBR encoding mode

CBR encoding mode

Fully customizable through runtime encoding settings

HRD CPB compliant CBR NAL output

Intra Refresh encoding mode available for sub-frame contribution to the end-to-end latency

On-the-fly bitrate changes supported

Error resilient encoding options

Multiple slices per frame encoding option

Motion vectors can be optionally constrained within slice boundaries

Deblocking filter can be optionally constrained within slice boundaries

Smooth System Integration

Full abstraction of the internal implementation details and the H.264 complexity from the top level I/O and its operation

Simple, microcontroller like, programming interface

High-speed, flow controllable, streaming I/O data interfaces

Simple and FIFO like

Avalon-ST compliant (ready latency 0)

AXI4-Stream compliant

Low requirements in external memory bandwidth

Flexible external memory interface

Independent of external memory type

Tolerant to latencies

Allows for shared memory access

Can optionally operate on independent clock domain

Trouble-Free Technology Map and Implementation

Fully portable, self-contained RTL source code

Strictly positive edge triggered design

D-type only Flip-Flops

Safe CDC transfers when using more than one clock domain

No special timing constraints required

No false or multi-cycle paths within the same clock domain

No CDC transfers that need to be constrained (all CDC paths can be excluded)

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