The H.264 video encoder IP cores for FPGA and ASIC designs from Alma Technologies stand out
for the compression efficiency and the perceptually optimized image quality they offer.
A very rich and well balanced feature-set is offered, along with six base
configurations and more than five key options to fine-tune each. Our portfolio
includes Baseline, Main and High profiles encoders, supporting 4:2:0 and 4:2:2
chroma sampling with up to 12-bit per component color depth.
The ITU-T H.264 recommendation, also known as Advanced Video Coding (AVC),
is an in-force video compression standard that was developed in response
to the growing need for higher compression of moving pictures. It has been
leading video applications to a new era for over 15 years.
Alma Technologies invested a great R&D effort to develop expertise and
produce this broad range of H.264 IP cores that perform exceptionally
well in a very broad range of applications and requirements.
These H.264 cores are remarkably easy to operate, ready to encode video right
out of the box. They have very simple and comprehensive video data and
programming interfaces. They accept uncompressed video data in planar,
interleaved, or macroblock scan format and output standalone, standard compliant,
Annex B NAL byte-stream.
Using the H.264 Encoder cores is simple via an intuitive interface
The H.264 cores from Alma Technologies are designed for easy integration in FPGA and ASIC designs.
The input and output data interfaces support streaming and allow the external logic to control the data flow.
The external memory interface is simple and flexible, with independent requests, read and write data paths.
It is also designed to be tolerant to memory delays and latencies, which may be present in
a shared memory system architecture.
Top Image Quality
No compromises that would decrease the image quality were made during the
development phase of the H.264 encoder cores. The silicon resource usage
is optimized, having always the best image quality in target.
An extensive research to optimize the coding was made and thousands of hours were invested
analyzing benchmark video sequences. As a result, we developed an especially efficient mode
selection algorithm and an advanced rate control algorithm based on run-time adaptive models
of content complexity and rate-distortion curves.
Our high-end H.264 encoders use a full search, variable block size, motion estimation engine with
¼ pixel accuracy. Excellent adaptability to temporal and spatial content variations is
enabled by quantization adjustments that are performed on a deep sub-frame basis.
High Performance & Low Power
Our H.264 encoders are designed to achieve high throughput with low clock frequencies.
The cores can fit and process Full HD video in low-cost FPGA device families.
For example, Full HD 1080p30 video can be encoded in real time using Intel Cyclone III/IV/V or
Xilinx Artix-7 devices. In modern ASIC implementations the cores support 4K UHD with remarkable
leakage and dynamic power figures.