JPEG-C
8-bit Baseline JPEG Codec with Optional Video Rate Control
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The JPEG-C core from Alma Technologies is a standalone and high-performance, half-duplex 8-bit Baseline JPEG Codec for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ITU-T T.81 JPEG standard makes this IP core ideal for interoperable systems and devices. The JPEG-C is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
![JPEG-C block diagram | Alma Technologies](site_db/pages/products/03_Image Compression IP/01_JPEG IP/05_JPEG-C/BlockDiagram.png)
In addition to the standard defined Baseline JPEG streams, the core is also capable of supporting the video payload of many (de facto) standard motion JPEG container formats. The JPEG-C can also be enhanced with an optional add-on bit-rate control block, which will benefit the bandwidth constrained applications.
The core is designed with easy-to-use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the JPEG-C is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
IP Deliverables
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts