8-bit Baseline JPEG Decoder
The JPEG-D core is a standalone and high-performance 8-bit Baseline JPEG decoder for still image and video compression applications. Compliance¹ with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes this IP core suitable for interoperable systems and devices. The JPEG-D is available for ASIC or Intel, Lattice, Microsemi and Xilinx FPGA and SoC based designs.
In addition to decoding standard Baseline JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.
The core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-D is a reliable and easy-to-use and integrate IP.
Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized and verified Netlist for Intel, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
|¹||Please refer to the Specifications tab for limitations with respect to the ISO/IEC 10918-1 JPEG standard.|