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8-bit Baseline JPEG Encoder with Optional Video Rate Control

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The JPEG-E core from Alma Technologies is a standalone and high-performance 8-bit Baseline JPEG encoder for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard makes this IP core ideal for interoperable systems and devices. The JPEG-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microsemi FPGA and SoC based designs.

In addition to generating standalone Baseline JPEG streams, this encoder can also produce the (de-facto) standard video payload of many motion JPEG container formats. Furthermore, the optionally included video rate control block is a best fit for the bandwidth constrained applications.

<nobr>JPEG-E</nobr> block diagram | Alma Technologies

The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-E is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.

IP Deliverables

Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Self checking testbench environment, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Specifications »

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