The Alma Technologies JPEG-E IP Core is a standalone and high-performance JPEG encoder for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard makes the JPEG-E core ideal for interoperable systems and devices.
In addition to generating standalone Baseline JPEG streams, the encoder can also produce the (de-facto) standard video payload of many motion JPEG container formats. Furthermore, the optionally included constant bitrate video rate control block is a best fit for the bandwidth constrained applications.
The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-E is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.
Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized and verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts