8-bit Baseline JPEG Encoder with Optional Video Rate Control
In addition to generating standalone Baseline JPEG streams, this encoder can also produce the (de-facto) standard video payload of many motion JPEG container formats. Furthermore, the optionally included video rate control block is a best fit for the bandwidth constrained applications.
The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces.
Being carefully designed, rigorously verified and silicon-proven, the
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts