The JPEG-E core from Alma Technologies is a standalone and high-performance 8-bit Baseline JPEG encoder for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard makes this IP core ideal for interoperable systems and devices. The JPEG-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.

In addition to generating standalone Baseline JPEG streams, this encoder can also produce the (de-facto) standard video payload of many motion JPEG container formats. Furthermore, the optionally included video rate control block is a best fit for the bandwidth constrained applications.

The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-E is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.

IP Deliverables

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Symbol

Features

Complete, Compliant and Standalone Operation

8-bit Baseline JPEG encoder with full ISO/IEC 10918-1 compliance

Up to 64K x 64K image resolution

1-4 image components

1, 2 and 4 horizontal and vertical sampling factors support

Single- and multi-scan support

Programmable Quantization Tables (up to four)

Programmable Huffman Tables (two DC, two AC)

Programmable Restart Markers insertion

Complete and standalone Baseline JPEG stream output with user controllable marker inclusion

CPU-less operation

Single clock cycle per sample encoding throughput

Extra Capabilities

Programmable Quality Factor (1 to 100) for easy Quantization Tables scaling

Motion JPEG payload encoding

Optional block-based maximum output size control with independent Luminance and Chrominance bit thresholds

Optional high-quality and accurate video rate control

Automatic Quality Factor adjustment per frame

Programmable nominal compressed frame size

Programmable bandwidth shaping output buffer size

Ease of Integration

Simple, microcontroller like, programming interface

High-speed, flow controllable, streaming I/O data interfaces

Simple and FIFO like

Avalon-ST compliant (ready latency 0)

AXI4-Stream compliant

Trouble-Free Technology Map and Implementation

Fully portable, self-contained RTL source code

Strictly positive edge triggered design

D-type only Flip-Flops

Fully synchronous operation

No special timing constraints required

No false paths

No multi-cycle paths

Literature

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JPEG-E IP CORE LICENSING OPTIONS

JPEG-E IP CORE LICENSING OPTIONS

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Additional Information
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ASICFPGAAMD-XilinxEfinixIntelLatticeMicrochip--- Enter Optional Text ---