UHT-DSC-D
Scalable Ultra-High Throughput DSC 1.2b Decoder
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The
The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.
The scalability of this IP core enables highly cost-effective silicon implementations of applications that need to handle massive pixel rates and resolutions.
The

The
IP Deliverables
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Extensive documentation
Bit Accurate Model (BAM) with optional Test Vector generation functionality
Self-checking testbench environment
Sample BAM scripts
Synthesis scripts
Simulation scripts
Place & Route scripts for FPGAs
Symbol

Features
VESA DSC 1.2b Compliant, Complete and Standalone Operation
Full compliance with the VESA DSC 1.2b specification
Backwards compatible with VESA DSC 1.1
RGB and YCbCr color space formats
8, 10, 12, 14 and 16 bits per color component dynamic range
Native support for 4:4:4, 4:2:2 and 4:2:0 sampling formats
Up to 16 slices per line
Scalable architecture with configurable number of internal, parallel decoding engines
1 pixel/clock per decoding engine processing for 4:4:4 sampling format
2 pixels/clock per decoding engine processing for 4:2:2 and 4:2:0 sampling formats
Operation without external memory
Very low internal memory requirements (a few image lines)
Ultra-low latency performance (sub-line latency)
CPU/GPU-less, complete and standalone implementation
Trouble-Free Technology Map and Implementation
Self-contained RTL design
No internal tri-states
Strictly positive edge triggered design
D-type only Flip-Flops
Fully synchronous operation per clock domain
Safe CDC transfers between clock domains
No need for special timing constraints
No false or multi-cycle paths within the same clock domain
No CDC transfers that need to be specially constrained
No other specially constrained timing paths