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Scalable Ultra-High Throughput VESA DSC 1.2b Encoder

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The UHT-DSC-E core from Alma Technologies is an advanced video encoder IP, compliant to the VESA Display Stream Compression (DSC) v1.2b standard. It supports encoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits sample depths.

The core is scalable and has been designed for enabling ultra-high throughput video encoding, even in medium-range target implementation technologies. It is available for ASIC and AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.

UHT-DSC-E block diagram | Alma Technologies

The UHT-DSC-E is designed using internal (on-chip) memory blocks only, with simple and fully controllable streaming input and output interfaces. It is a complete and autonomous encoder, not needing any host system CPU or GPU support for its operation. Being carefully designed and rigorously verified, the UHT-DSC-E is a reliable and easy-to-use and integrate IP core.

IP Deliverables

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Specifications »

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