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UHT-JPEG-D

Scalable UHD JPEG Decoder − Ultra-High Throughput, 8/10/12-bit per component

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Features

High-Performance, Compliant and Standalone Operation

Ultra high throughput in low-end silicon using scalable and transparent parallel processing

ITU T.81 compliance¹

4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video data decoding

8-, 10- and 12-bit per component sample depth

Single JPEG byte stream input and single - multiple pixels - raster scan interleaved output

Motion JPEG payload decoding

CPU-less, complete and standalone operation


Advanced Implementation

Up to 32 samples per clock cycle decoding

Algorithmic decoding latency of approximately 32 scan lines for 4:2:0 and 16 scan lines for all other sampling formats

Configurable full on-chip or mixed on/off-chip memories implementation

Flexible optional off-chip memory interface

Independent of external memory type

Tolerant to latencies

Allows for shared memory access

Can optionally operate on independent clock domain

Avalon-ST and AXI4-Stream compliant streaming data I/O


Trouble-Free Technology Map and Implementation

Fully portable, self-contained RTL source code

Strictly positive edge triggered design

D-type only Flip-Flops

Safe CDC transfers when using more than one clock domain

No special timing constraints required

No false or multi-cycle paths within the same clock domain

No CDC transfers that need to be constrained
(all CDC paths can be excluded)


Limitations Applying When Using a Third-Party JPEG Encoder¹

Single decoding engine operation may be needed

Single scan interleaved JPEG format only

The image dimensions declared in the SOF marker must be an integer multiple of 8

No DNL marker



Notes :
¹Decoding of corrupted bitstreams, with or without restart segments, is not supported.


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