UHT-JPEG-E
Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
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This ultra-fast JPEG encoder IP core is fully compliant to the ITU T.81 specification and supports encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) images or video streams,
in 8-, 10- or 12-bit per component color depth. The

Using multiple internal processing engines, the
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The
IP Deliverables
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Symbol

Features
High-Performance, Compliant and Standalone Operation
Ultra high throughput in low-end silicon using scalable and transparent parallel processing
Full ITU T.81 compliance
4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video input
8-, 10- and 12-bit per component sample depth encoding
Single - multiple pixels - raster scan interleaved input and single, ready-to-use, JPEG byte stream output
Motion JPEG payload encoding
CPU-less, complete and standalone operation
Advanced Implementation
Up to 32 samples per clock cycle encoding
Algorithmic encoding latency of approximately 32 scan lines for 4:2:0 and 16 scan lines for all other sampling formats
CQP - VBR encoding mode with programmable Quality Factor (1 to 100)
Constant Bitrate (CBR) video encoding mode
Programmable output frame size
Programmable transmission buffer size
On-the-fly video bitrate changes supported
Configurable full on-chip or mixed on/off-chip memories implementation
Flexible optional off-chip memory interface
Independent of external memory type
Tolerant to latencies
Allows for shared memory access
Can optionally operate on independent clock domain
Avalon-ST and AXI4-Stream compliant streaming data I/O
Trouble-Free Technology Map and Implementation
Fully portable, self-contained RTL source code
Strictly positive edge triggered design
D-type only Flip-Flops
Safe CDC transfers when using more than one clock domain
No special timing constraints required
No false or multi-cycle paths within the same clock domain
No CDC transfers that need to be constrained
(all CDC paths can be excluded)
Literature
(No registration required)