The UHT-JPEG2K-E core from Alma Technologies is a scalable, ultra-high throughput, hardware JPEG 2000 encoder, designed to provide all the power needed in modern image and Ultra HD video compression applications that have to cope with massive pixel rates and resolutions. This IP core supports lossy and numerically lossless encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) images or video streams with up to 16-bit per component color depth. The UHT-JPEG2K-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.

Using multiple internal compression engines, the UHT-JPEG2K-E offers the needed performance through its scalable parallel architecture. Each input image or video frame is split internally into pieces and each piece is allocated to one of the multiple internal compression engines. The encoded output streams of the compression engines are combined in a single output stream. These operations are done in a way that is transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components. The number of internal compression engines is configurable before synthesis, adapting to the implementation technology speed, and non-critical resources are shared between the multiple compression engines.

The UHT-JPEG2K-E IP Core is very easy to use and integrate in a system. A single uncompressed data input interface is used to accept raster scan pixels, and a single JPEG 2000 compliant byte stream is produced to the output. The operation of the core is completely standalone, without needing any host CPU or GPU power. The JPEG 2000 output byte stream can be decoded - as is - by any corresponding ISO/IEC 15444-1 JPEG 2000 compliant decoder.

The UHT-JPEG2K-E core features simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed and rigorously verified, the UHT-JPEG2K-E is a reliable, easy-to-use and integrate IP providing a best value solution for your FPGA or ASIC design.

IP Deliverables

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Symbol

Features

ISO/IEC 15444-1 Compliant and Standalone Operation

Full compliance to the ISO/IEC 15444-1 JPEG 2000 specification

4:4:4, 4:2:2, 4:2:0 and 4:0:0 encoding

8 up to 16 bits sample depth encoding

Up to 65535 x 65535 image resolution

Up to 8192 x 8192 tile resolution

Lossless or lossy compression

Advanced rate control engine

ISO/IEC 15444-1 compliant code stream (JPC) or file (JP2) JPEG 2000 output

CPU-less, complete and standalone operation

Advanced JPEG 2000 Implementation

Ultra-high throughput in medium-end silicon

Superior compression and video quality from ED to Ultra HD resolutions

CBR image/video encoding mode

Rate control option with programmable requested output compression ratios

On-the-fly nominal output compression ratios changes are supported

Medium requirements in external memory bandwidth

Flexible external memory interface

Independent of external memory type

Tolerant to latencies

Allows for shared memory access

Can optionally operate on independent clock domain

Easy Implementation and Verification

Extensive documentation

Bit Accurate Model (BAM) with optional Test Vector generation functionality

Self-checking testbench environment

Sample BAM scripts

Synthesis scripts

Simulation scripts

Place & Route scripts for FPGAs

Trouble-Free Technology Map and Implementation

Fully portable HDL source code

No internal tri-states

Strictly positive edge triggered design

D-type only Flip-Flops

Fully synchronous operation

Safe CDC transfers

No need for special timing constraints

No false or multi-cycle paths within the same clock domain

No CDC transfers that need to be constrained

No specially constrained timing paths

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UHT-JPEG2K-E IP CORE LICENSING OPTIONS

UHT-JPEG2K-E IP CORE LICENSING OPTIONS

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ASICFPGAAMD-XilinxEfinixIntelLatticeMicrochip--- Enter Optional Text ---