The UHT-JPEGLS-E core is a JPEG-LS encoder, compliant to ISO/IEC IS 14495-1 | ITU-T Recommendation T.87 standards. It supports encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) video streams, in 8 up to 16 bits sample depths. The core is a standalone and high-performance JPEG-LS encoder, designed for enabling ultra-high frame rate SD and HD encoding, and Ultra HD video encoding (4K/8K and beyond), even in low-end ASIC or FPGA silicon. The UHT-JPEGLS-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.

JPEG-LS is based on the LOCO-I (Low Complexity-Lossless Compression for Images) image compression algorithm, which uses a non-linear predictive scheme with rudimentary edge detecting capability, based on the four nearest –causal- neighbours (left, upper left, upper and upper right) and an entropy encoder using adaptively selective Golomb-type codes. The low complexity scheme of JPEG-LS is based on the assumption that prediction residuals follow a two-sided geometric distribution and the fact that Golomb-codes are optimal for geometric distributions, thus the modeling and coding units are matching.

UHT-JPEGLS-E is very easy to use and integrate in a system. It requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can encode an arbitrary number of video frames without the need of any further intervention or assistance by the host system CPU.

UHT-JPEGLS-E accepts the uncompressed raw video data in interleaved scan format. It outputs standalone, standard compliant, JPEG-LS byte stream format. No post processing on the output stream, other than (as examples) saving, muxing, or transmitting, is required by the host. The output JPEG-LS byte stream can be decoded, as is, by any corresponding ISO/IEC IS 14495-1 | ITU-T Recommendation T.87 compliant decoder.

IP Deliverables

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Symbol

Features

ISO/IEC IS 14495-1 JPEG-LS T.87 Compliant and Standalone Operation

Full compliance to the ISO/IEC IS 14495-1 JPEG-LS specification

Programmable image dimensions from 8 x 8 up to 64k x 64k

4:4:4, 4:2:2, 4:2:0 and 4:0:0 single scan encoding

8 up to 16 bits per sample depth encoding

Programmable point transform

Programmable local gradient thresholds

ISO/IEC IS 14495-1 compliant JPEG-LS byte stream output

CPU-less, complete and standalone operation

Advanced JPEG-LS Implementation

Ultra-high throughput in low-end silicon

Low native encoding latency

On-chip memory implementation

Easy Implementation and Verification

Extensive documentation

Bit Accurate Model (BAM) with optional Test Vector generation functionality

Self-checking testbench environment

Sample BAM scripts

Synthesis scripts

Simulation scripts

Place & Route scripts for FPGAs

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UHT-JPEGLS-E IP CORE LICENSING OPTIONS

UHT-JPEGLS-E IP CORE LICENSING OPTIONS

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ASICFPGAAMD-XilinxEfinixIntelLatticeMicrochip--- Enter Optional Text ---