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CCSDS-122-E

CCSDS 122.0-B-1 Encoder - Lossless and Lossy Image Data Compression with up to 16 bits Pixel Dynamic Range

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CCSDS-122-E Symbol | Alma Technologies


Features

CCSDS 122.0-B-1 Compliant, Complete and Standalone Operation

Full compliance to the CCSDS 122.0-B-1 specification

Numerically lossless or lossy compression

Up to 16 bits pixel dynamic range

Both integer and float 9/7 DWT

Integrated rate control

Operation without external memory

CPU/GPU-less, complete and standalone implementation


Smooth System Integration

Full abstraction of the internal implementation and CCSDS122.0-B-1 details from the top level I/O and its operation

Simple, microcontroller like, programming interface

High-speed, flow controllable, streaming I/O data interfaces

Simple and FIFO like

Avalon-ST compliant (ready latency 0)

AXI4-Stream compliant

Designed for both FPGA and ASIC implementations with user configurable architecture before synthesis

Configurable maximum supported image width

Configurable maximum supported pixel dynamic range (up to 8-, 12- or 16-bit)

Configurable DWT filter(s)

Integer only

Float only

Both integer and float


Trouble-Free Technology Map and Implementation

Fully portable, self-contained RTL source code

Strictly positive edge triggered design

D-type only Flip-Flops

Fully synchronous operation

No special timing constraints needed

No false or multi-cycle paths



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