Lossless and Lossy JPEG 2000 Encoder
The JPEG2K-E core is a still image and video encoder that implements Part 1 of the JPEG 2000 standard. It offers up to 16-bit per component Numerically Lossless or Lossy compression, including advanced - high-quality and extremely accurate - rate control functionality. The JPEG2K-E can also optionally include support for single-component Multiple Quality Layers encoding in LRCP progression order. It is available for ASIC or Intel, Lattice, Microsemi and Xilinx FPGA and SoC based designs.
The JPEG 2000 compression standard offers an advanced quality and feature set, lending itself to a wide range of uses from digital cameras through to space imaging and other key sectors. Full compliance to the ISO/IEC 15444-1 JPEG 2000 standard makes the JPEG2K-E core ideal for interoperable systems and devices.
The JPEG2K-E supports up to 64K x 64K image resolution using up to 8K x 8K tiles. It is a highly scalable IP before synthesis regarding encoding throughput and corresponding silicon implementation area. The JPEG2K-E includes also an advanced post-compression, rate-distortion optimized, rate control engine which provides full control over the required bandwidth on the JPEG 2000 stream output. The bitrate of the JPEG 2000 stream can be accurately adjusted while, at the same time, preserving the maximum image fidelity that is possible within the available bandwidth constraints.
The JPEG2K-E core implements a simple but yet flexible, requests based, external memory interface with independent read and write data paths. This makes the JPEG2K-E independent of memory type supporting, for example, operation with SRAM, SDRAM, DDR, DDR2 and DDR3 types of memory. JPEG2K-E is designed to be tolerant to memory delays and latencies, which may be present on shared memory system architectures.
The core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG2K-E is a reliable and easy-to-use and integrate IP.
Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for Intel, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts