The UHT-H264E-LME core from Alma Technologies is a compact, ultra-high throughput, scalable, hardware H.264 encoder with a Light Motion Estimation engine,
designed to enable 4K and 8K Ultra HD resolutions in power- and cost-effective FPGA or ASIC implementations.
Equipped with its very compact Light Motion Estimation engine, this member of our
UHT H.264 IP cores family best suits area critical
applications that need a medium level of compression, or work with video content that has low motion
complexity. Encapsulating the longstanding Alma Technologies expertise with H.264, this encoder offers
perceptually optimized image quality and includes valuable technology, such as its high-quality,
low-latency, Intra-Refresh based encoding option.
The UHT-H264E-LME can be configured to support Baseline, Main and High profiles, 4:2:0 and 4:2:2 chroma sampling,
and up to 12-bit per component color depth. It can be also used for high frame rate SD to Full HD interlaced
or progressive video encoding. The core is very easy-to-use and integrate in a system. It is an autonomous,
CPU/GPU-less, complete H/W implementation, accepting video input in standard raster scanned interleaved order
and producing ready-to-use H.264 NAL byte-stream output.
The UHT-H264E-LME is based on a scalable architecture that uses a configurable number of internal, parallel processing, engines.
This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization
complexity from the rest SoC design and operation. In addition to the configurable number of internal engines that matches
the throughput requirements to the available silicon speed, the encoder can be further fine-tuned before synthesis to save
silicon area by removing features that are not needed in a certain implementation.
The UHT-H264E-LME core implements a simple and flexible, requests based, external memory interface with independent read and
write data paths. The external memory I/F is also designed to be tolerant to memory delays and latencies, which may be
present in a shared memory system architecture.
Being carefully designed and rigorously verified the UHT-H264E-LME is a reliable and easy-to-use and integrate IP.
Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
Self-checking testbench environment sources, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts