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UHT-H264E-LME

Scalable UHD H.264 Encoder − Ultra-High Throughput, Light Motion Estimation

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Features

Standard Compliant and Standalone Operation

Full compliance to the ITU-T H.264 specification

Constrained Baseline, Main, High 10, High 10 intra, High 4:2:2, High 4:2:2 intra, High 4:4:4 (12 bit 4:2:2 or 4:2:0), and High 4:4:4 intra (12 bit 4:2:2 or 4:2:0) profiles encoding

4:2:0 and 4:2:2 YCbCr digital video input

8-, 10- and 12-bit per component color depth encoding

ITU-T H.264 Annex B compliant NAL byte-stream output

Profile Level up to 5.2

No host CPU assisted, autonomous operation


Advanced H.264 Implementation

Perceptually optimized Image Quality

Ultra-High throughput using scalable and transparent parallel processing

Very compact silicon footprint Light Motion Estimation engine

Advanced Intra prediction

All 4 Intra 16x16 prediction modes

All 4 Intra Chroma prediction modes

All 9 Intra 4x4 prediction modes

Intra in P (all prediction modes are always examined)

CABAC or CAVLC entropy coding

CQP - VBR encoding mode

CBR encoding mode

One frame algorithmic encoding latency

Intra-Refresh encoding mode available for zero additional latency contribution to the end-to-end system latency

On-the-fly bitrate changes supported

Multiple slices per frame encoding


Smooth System Integration

Full abstraction of the internal implementation details and the H.264 complexity from the top level I/O and its operation

Simple, microcontroller like, programming interface

High-speed, flow controllable, streaming I/O data interfaces

Simple and FIFO like

Avalon-ST compliant (ready latency 0)

AXI4-Stream compliant

Low requirements in external memory bandwidth

Flexible external memory interface

Independent of external memory type

Tolerant to latencies

Allows for shared memory access

Can optionally operate on independent clock domain


Trouble-Free Technology Map and Implementation

Fully portable, self-contained RTL source code

Strictly positive edge triggered design

D-type only Flip-Flops

Safe CDC transfers when using more than one clock domain

No special timing constraints required

No false or multi-cycle paths within the same clock domain

No CDC transfers that need to be constrained (all CDC paths can be excluded)



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